(1) Technical Field
This invention generally relates to electronic circuitry, and more specifically to frequency dividers suitable for use in phase locked loops and frequency synthesizers.
(2) Background
A phase locked loop (PLL) is an electronic feedback control system that generates an output frequency Fout having a phase that is related to the phase of an input reference frequency Fref. A typical PLL compares the phases of two input frequencies, Fc and Fp, in a phase detector, which produces an error signal e(s) that is proportional to the difference between the phases of the input frequencies. The error signal is then loop filtered and used to drive a variable frequency oscillator, typically a voltage controlled oscillator (VCO), which creates the output frequency Fout. The output frequency Fout is fed through a feedback divider back to the input of the system as Fp, producing a negative feedback loop. If the output frequency Fout drifts, the phase error signal e(s) will increase, driving the output frequency Fout in the opposite direction so as to reduce the error. The other input frequency, Fc, is derived by dividing down a reference frequency Fref, usually derived from a very stable frequency source, such as a crystal oscillator.
PLLs have numerous applications in the field of electronics, including as frequency synthesizers in radio systems.
It is desirable in many applications, and especially in radio frequency (RF) based applications, that the noise levels of a PLL be low. In particular, it is desirable to reduce phase noise, a well-known characteristic of oscillator-based circuits. The present invention addresses these needs.